A 500-mA Dual-Mode NMOS Output-Capacitorless LDO with a High-Frequency Transient Detection Technique for 5-ns Edge Times

Modern power management integrated circuits (PMICs) for advanced systems-on-chip (SoCs) heavily rely on output-capacitorless (OCL) low-dropout (LDO) regulators to minimize printed circuit board (PCB) footprint and cost. However, achieving rapid transient responses during severe load fluctuations remains a critical challenge, particularly for waking up power-gated on-chip domains. This article proposes a wide-load-range OCL-LDO regulator achieving a fast transient response under extreme 5-ns edge-time load transition conditions, utilizing an adaptive mode-switching technique based on high-frequency transient detection. In steady state, the proposed LDO minimizes quiescent current while maintaining a high DC loop gain of 90.6–103.7 dB to ensure tight regulation. Upon detecting a rapid load transition, the circuit instantaneously switches to an active-state loop, which prioritizes high bandwidth and slew rate over DC gain. Consequently, the proposed architecture ensures stability up to a 500-mA load, achieving a phase margin over 60° across most of the operating range. The prototype, fabricated in a standard 180-nm CMOS process, regulates a 1.2-V input to a 1.0-V output. Using an on-chip load switch to generate the 5-ns load edge in the present measurement setup, the prototype achieves a measured settling time of 132 ns for a 1-to-500-mA load step, targeting the wake-up of on-chip power domains in SoCs.