A Capacitively Coupled Dual-Gate 2D Transistor Unifying Logic-in-Memory and Tunable Synaptic Plasticity

Abstract Integrating logic control with adaptive synaptic learning at the device level is a key step toward high-performance computing-in-memory (CIM) hardware. However, the integration of logic-in-memory (LIM) and synaptic plasticity within a homogeneous device is hindered by the incompatibility between stable logic output and dynamic weight modulation. Here, we demonstrate a logic-synapse function-integrated device based on a two-dimensional (2D) floating-gate field-effect transistor (FGFET) with a coplanar dual-control-gate architecture. With two independent gate-coupling coefficients, the nominally symmetric design allows the gate-induced potential increments to superpose on the floating gate: cooperative inputs induce charge tunneling and write a new memory state, whereas antagonistic inputs approximately cancel the pulse-induced potential increment and latch the stored state. This rule directly implements LIM within a single device, enabling 14 reconfigurable Boolean logic operations with in situ nonvolatile output storage, a logic read margin of 104, and no external cascading for the demonstrated two-input logic functions. The same coupling framework further supports tunable synaptic plasticity, including lateral enhancement/inhibition and spatiotemporal competition/cooperation among multiple synaptic inputs. In particular, asynchronous competitive modulation modifies history-dependent conductance updates, improving the depression nonlinearity to 0.0833 while retaining a dynamic range of 22.82. These results establish an all-electrical device-level route for integrating logic control and neural weight adaptation in compact CIM hardware.