Area-optimized crossover-free n-bit coplanar ripple carry adder in quantum-dot cellular automata

Abstract Quantum-Dot Cellular Automata (QCA) provides a potential post-CMOS platform for compact and low-power arithmetic circuits. This paper presents compact and area-conscious coplanar n-bit Ripple Carry Adder (RCA) architectures based on a modified and structurally optimized QCA full adder cell derived from a previously reported design. The modified full adder cell is used as a reusable building block to develop and systematically evaluate crossover-free coplanar 2-bit, 4-bit, and 8-bit RCA architectures. The full adder cell requires 14 cells, occupies an extent of 0.014 μm², and achieves a quantum cost of 0.0078 with a latency of 0.75 clock cycles. The resulting 2-bit, 4-bit, and 8-bit RCAs require 64, 118, and 376 cells, respectively, with occupied extents of 0.09, 0.15, and 0.56 μm² and latencies of 1.50, 2.00, and 3.75 clock cycles, respectively, without crossover structures. Relative to the evaluated state-of-the-art baselines, the 4-bit and 8-bit RCAs achieve average reductions of 85.40% and 64.53% in cell intricacy and 96.83% and 76.64% in quantum cost, respectively. Energy-dissipation analysis using QCADesigner-E further characterizes the proposed architectures, while direct comparison with literature energy values is treated cautiously because of differences in estimation methodologies. The crossover-free organization supports compact and regular arithmetic realization; however, the present study is limited to QCA simulation, physical and energy estimation, and architectural comparison. Potential relevance to ML-oriented nano-computing is discussed conceptually and is not validated through direct ML workload implementation or physical fabrication.