600 °C selective epitaxial growth of SiGe:B for FD-SOI devices

The 600 °C Selective Epitaxial Growth (SEG) of SiGe:B layers was investigated, the aim being to fabricate Raised Sources and Drains (RSDs) on each side of p-type Metal Oxide Semiconductor Field Effect Transistors. We indeed strove to decrease by 50 °C the growth temperature compared to our 650 °C reference process in order to benefit from higher active boron concentrations, e.g. lower electrical resistivities. A co-flow approach with a chlorinated chemistry was used. Two processes were investigated: Process 1 at 20 Torr and Process 2 at 10 Torr. They were tailored in terms of mass-flows in order to obtain full growth selectivity and superior crystalline quality SiGe:B layers with Ge contents in the 30-35% range. We first assessed the impact, of the gaseous precursor flows (SiH 2 Cl 2 , GeH 4 , HCl, B 2 H 6 ) and of the H 2 carrier flow on growth kinetics, morphologies, electrical resistivities and boron concentrations in blanket SiGe:B films. In a second part, those processes were evaluated on patterned Fully Depleted – Silicon-On-Insulator (FD-SOI) substrates. Selectivity, morphologies and loading effects were quantified depending on the B 2 H 6 and HCl flows. Those 600 °C SEG SiGe:B processes yielded lower electrical resistivities, around 0.51-0.53 mΩ cm, than the 650 °C reference process giving an electrical resistivity of 0.75 mΩ cm. This study highlighted the interest of lowering the growth temperature during the SEG of SiGe:B with a co-flow approach; the incorporation of electrically active dopants in the substitutional sites of the SiGe:B lattice was then higher.