Mitigating Refractory Blindness and Somatic Freezing in Dense Neuromorphic Vision Processors via an Asymmetric Input Funnel Architecture and NVIDIA GPU Co-Design

Second-order Current-Based (CUBA) Leaky Integrate-and-Fire (LIF) circuits form the foundation of low-power neuromorphic spiking hardware. However, when interfacing directly with high-temporal-resolution Dynamic Vision Sensors (DVS), unconstrained afferent event storms induce severe dynamical failure modes: integer bit-width wrapping, subtractive brake echo latchup, and subnegative somatic freezing. While Adaptive Threshold LIF (ALIF) attempts to regulate runaway somatic excitation, dynamic threshold expansion requires continuous memory read-modify-write bandwidth and wide comparator banks without shielding dendritic entry registers. This paper presents an Asymmetric Input Current Funnel Shunting Architecture combined with an NVIDIA PyTorch-native CUDA software co-design framework. The system confines all dynamic attenuation, saturation bounding, and reactive shunting to the channel entry gate (u1) while anchoring the somatic threshold comparator to a static transistor rail (Vth = –55.0 mV). The architecture integrates four operational mechanisms: (1) an edge-triggered Synchronous Zero-Flush Register, (2) a Gated Rectified Linear Current Sink with strict non-negative projection, (3) a Dimensionally Scaled Coupling Accumulator, and (4) a Soft-Bounded Bidirectional STDP Engine with homeostatic L1 conductance budgeting implemented via power-of-two barrel shifts. Validated through GPU-accelerated PyTorch tensor simulations and synthesizable two-stage pipelined Verilog across a comprehensive verification battery, the core eradicates the Sensory Blindness Duty Cycle (0.0% vs. 99.5% in unshielded baselines), guarantees zero arithmetic overflows under 100% storm saturation, bounds maximum firing to a 34% duty cycle, and achieves instant recovery from quiescent intervals. Gate-level logic synthesis reveals a low-overhead footprint of 35 flip-flops and 1,385 combinational gate primitives.