High-performance charge balanced double p-layer double lateral gate vertical power MOSFET

This paper proposes a novel additional P layer added in the drift region of the single stack laterally orientated double gate trench vertical power MOSFET structure. The construction employs a single P layer surrounded by SiO 2 insulator from three side and N-epi drift region from one side, organized with another additional P-layer sandwiched between the two lateral gates, near the channels. The two lateral polysilicon gates with a P-layer sandwiched between them, along with channels, represent a single stack. In addition, the P-layer in the drift region modulates the electric field distribution, resulting in an effective improvement in the breakdown voltage. The dimension and doping of the added drift region p-layer is optimized to provide the maximum BV, finest figure of merits and optimum Ron-BV tradeoff. The proposed device exhibits favorable breakdown characteristics without altering the doping concentration of the drift region and channel dimensions. Results show the perfect charge balance is achieved in p–n active area, represented by P type layer and n type drift region, at Wt/Wp ratio of 1.5. The proposed P added double gate device exhibits lower gate to drain charge and capacitance, along with high BV and improved figure of merits. This reflects the low gate coupling in our proposed technology compares to its conventional power MOSFET. The simulation outcomes from the Silvaco TCAD device simulator demonstrate that the proposed device displays an exceptionally high breakdown voltage of 78.6 V, low FOM2, 3.88-fold enhancement in FOM1, with low specific ON resistance of 0.386 mΩ cm 2 .