Physics-aware and uncertainty-guided deep learning-based surrogate optimization for low-power OTA design

This paper presents a physics-aware and uncertainty-guided surrogate optimization framework for the design of ultra-low-power and low-noise cross-coupled feed-forward (CCFF) operational transconductance amplifiers (OTAs) for biosignal acquisition systems. Designing such OTAs involves complex trade-offs among gain, bandwidth, noise, and power, which are difficult to address using conventional methods. To overcome these challenges, a deep learning-based surrogate modeling framework implemented in PyTorch neural networks is proposed, explicitly incorporating device-level constraints such as $$g_m/I_D$$ , intrinsic gain ( $$g_m/g_{ds}$$ ), and saturation margins. This integration ensures physically consistent and manufacturable solutions while enabling efficient exploration of the design space. The proposed model simultaneously predicts gain, bandwidth, input-referred noise (IRN), and power consumption with high accuracy ( $$R^2$$ up to 0.9976). Uncertainty estimation using deep ensembles provides well-calibrated confidence bounds and strong correlation with prediction error, enabling risk-aware optimization. Multi-objective optimization using NSGA-II produces a well-distributed Pareto front, achieving gain up to 79 dB, bandwidth up to 11 kHz, IRN as low as 2.02 $$\mu$$ V $$_{\textrm{rms}}$$ , and power consumption down to 5.6 $$\mu$$ W. The results indicate that the surrogate model can reliably replace computationally expensive circuit simulations during optimization. Comprehensive validation across process corners confirms robust performance and stability, with all designs satisfying practical constraints. Compared to conventional analytical, $$g_m/I_D$$ -based, and surrogate-based approaches, the proposed framework provides improved trade-off exploration, robustness, and physical interpretability. This work establishes a scalable methodology that bridges physics-based design and data-driven optimization, offering a scalable and computationally efficient solution for next-generation low-power analog circuit design.