CryoModel-4K: physics-based BSIM4 extension for 28 nm bulk CMOS compact modeling at 4 Kelvin

Abstract Accurate compact transistor models for 28 nm bulk CMOS at cryogenic temperatures are essential for reliable quantum computing interface circuit design. Existing room-temperature BSIM4 models fail to capture carrier mobility freeze-out, subthreshold swing saturation, current kink effects, and threshold voltage shifts at 4 K. These failures produce post-fabrication performance deviations exceeding 300% in cryo-CMOS circuits designed using room-temperature models. This paper presents CryoModel-4K, a physics-based compact model that extends BSIM4 to accurately capture 28 nm bulk CMOS behavior from 300 to 4 K through three integrated correction modules. The Phonon Freeze-Out Mobility Enhancement Module (PFMEM) models the 3 to 8× carrier mobility enhancement at liquid helium temperatures through a Matthiessen’s-rule combination of phonon, impurity, and surface roughness scattering. It is validated against published 4 K Hall effect measurements. The Cryogenic Subthreshold Swing Saturation Model (CSSM) replaces the classical kT/q thermal voltage with a band-tail tunneling-corrected expression. It accurately reproduces the observed 15 to 25 mV/dec subthreshold swing plateau below 30 K. The Impurity Band Transport Kink Model (IBTK) captures the characteristic drain current kink arising from impact ionization triggered floating body effects in the partially frozen bulk substrate. Validation against published wafer-level characterization data for TSMC 28 nm bulk CMOS spanning 300 to 4 K across 380 devices on three wafer splits demonstrates less than 5% RMS prediction error for all DC characteristics and less than 8% for RF S-parameters up to 10 GHz. Ring oscillator frequency is predicted within 6.2% of measured values at 4 K, compared to 312.5% error for standard BSIM4. The total SPICE simulation overhead relative to standard BSIM4 is approximately 25%.