Electrical noise in NanoSheet FET in presence of interface traps: A reliability perspective in circuit application

This work investigates the reliability analysis of Interface Trap Charges (ITCs) and noise on various electrical parameters of NanoSheet FET (NSFET) using different channel materials. Simulations are carried out through 3D Sentaurus TCAD simulator under no trap, Uniform trap, and Gaussian trap conditions at the channel/SiO 2 interface considering three different electrical noise, viz. Diffusion, Generation Recombination (GR) and Flicker noise concludes that the proposed device is less prone to ITCs and noise. The analysis reveals that the dominancy is shown by GR and Flicker noise at low frequency range, while at high frequency, Diffusion noise becomes prepotent. A 1.2% drop in g m is noticed, when ITCs exists. Finally, circuit analysis is done using the NSFET in CMOS inverter and Common Source (CS) amplifier to understand more on the performance of the device in analog/ RF domain. A very minimal change in the gain of Inverter (3.37%) and CS amplifier (3.7%) is obtained, when traps are considered which makes the device suitable in nanoelectronics.