Dielectric Engineering for Sub-Nanometer Equivalent Oxide Thickness in Double-Gate WS2-FETs Using All-ALD-HfO2/ h -AlN Gate Stacks

Abstract This study reports a gate stack composed of an ultrathin epitaxial hexagonal aluminum nitride (h-AlN) interfacial layer (IL) deposited by plasma-enhanced atomic layer deposition (PEALD) between hafnium oxide (HfO2) and a monolayer tungsten disulfide (WS2) channel. The inherently inert surfaces of two-dimensional (2D) materials have hindered the deposition of ultrathin IL by ALD. By optimizing the h-AlN growth conditions and incorporating an in situ H2 cleaning process, a high-quality epitaxial h-AlN interfacial layer was achieved on monolayer WS2. Combined with subsequent HfO2 thickness scaling, the optimized gate stack achieved an extracted EOT of 0.68 ± 0.22 nm while maintaining a low gate leakage current density of 10–2 A/cm2, meeting the 2028 standards for low-power transistors in the International Roadmap for Device and Systems (IRDS). Furthermore, the fabricated HfO2/h-AlN/WS2 dual-gate (DG) field-effect transistors (FETs) exhibited low subthreshold swing (SS), near-zero hysteresis, and excellent electrostatic gate control.