Design of energy efficient display router employing advanced extensible interface synchronizer and clock gating techniques

The increasing need for high resolution, multi-functional displays in smart devices has paved the way for efficient data routing and power management between the host processor and multiple display modules. Existing solutions generally struggle to maintain low power consumption, high-speed data transfer and face issues in handling complex data prioritization. The proposed router architecture overcomes these limitations with the introduction of a prioritized, clock-synchronized and Advanced extensible interface (AXI)-compatible solution to provide efficient data distribution to multiple displays with reduced power overhead. The suggested architecture comprises of a Priority-based Finite State Machine (P-FSM), which performs clock selection and data prioritization for the input display data. It is further routed through an AXI-Synchronizer for assuring energy-efficient communication with high throughput. The synchronized and prioritized data is further provided to an Adaptive Intelligent Virtual Random Access Memory (AI_Virtual_RAM) register which acts as a centralized buffer and controller for routing. This register interfaces with multiple AI-display selection FIFO buffers regulated by clock control modules. In these modules, the clock related to the actively used display is enabled while the clocks for inactive display paths remain disabled which in turn reduces unnecessary power consumption and memory access significantly. By lowering dynamic power to 128 mW and increasing clock-gating efficiency to 72%, the architecture outperforms benchmark routers in terms of operational frequency (146.3 MHz), throughput (612 Mbps) and latency (21.3 ns). The proposed architecture thus contributes to optimized routing of display data with reduced power consumption and latency for flexible and efficient display interfacing.