RAPNet: Efficient Near-Sensor Radar Data Pre-Processing via DFT-to-GEMM Mapping

Radar is ubiquitous in many domains such as automotive. Modern radar sensors generate large amounts of data that needs to be moved from sensor nodes to Processing Units (PUs). In general, data movement incurs high power consumption and latency. To reduce data movement, processing near the radar sensor nodes is desirable. This paper employs a near-sensor processing approach that replaces dedicated Fast Fourier Transform (FFT) hardware with a reusable PU consisting of a general-purpose processor and a systolic array accelerator. The PU can perform both Discrete Fourier Transform (DFT) computation and Deep Neural Network (DNN) inference, allowing radar pre-processing and downstream perception to share the same hardware. We leverage this architecture to introduce RAdar Pre-processing Net (RAPNet), which maps Range-Doppler pre-processing to real-valued general matrix multiplication (GEMM) operations executed on the systolic array. This mapping allows the same accelerator to perform both radar pre-processing and downstream perception, enabling hardware reuse, the folding of radar-specific operations, task-aware optimization, and hardware/software co-design of lightweight pre-processing architectures. RAPNet replaces FFT-based pre-processing without reducing downstream task performance, and joint optimization improves selected task metrics. A PU based on RAPNet avoids approximately 4mm 2 of dedicated FFT cell area. Co-design of pre-processor and PU reduces the complete-frame pre-processing latency by 19.1% relative to the evaluated FFT accelerator, while retaining task metrics within four percentage points.