A compact and component-optimized 13-level switched-capacitor multilevel inverter with high efficiency

Switched-Capacitor Multilevel Inverters (SCMLIs) provide a viable pathway to achieving high-quality voltage synthesis with reduced reliance on magnetic components; however, existing 13-level implementations typically require a high number of switching devices and exhibit elevated total standing voltage (TSV), complicating semiconductor selection and gate-drive design. This paper introduces a compact 13-level switched-capacitor inverter that synthesizes thirteen symmetrical output levels using eleven switches, two capacitors, and two diodes supplied by two DC sources. The proposed configuration employs a structured switched-capacitor network that enables a practical voltage gain of 1.5 and ensures intrinsic capacitor self-balancing without auxiliary circuits or sensing hardware. A Phase-Disposition Pulse-Width Modulation (PDPWM) scheme was adopted for deriving gating signals and achieving accurate stepped waveform generation. Comprehensive simulation and experimental evaluations validated the correct operation of the inverter, demonstrating stable capacitor voltages and reliable performance under resistive, inductive, and time-varying load conditions. Experimental results show a low output-voltage total harmonic distortion of 0.61% and a high peak efficiency of 98.3%. Furthermore, measured switch blocking voltages confirm a reduced TSV of 4.88 Vdc, highlighting the potential of the proposed inverter for compact, efficient, and grid-connected medium-voltage functions.