Low-Power Cascadable STMG Full-Adder Architecture Without Carry Regeneration

This paper presents a design-optimization technique for cascadable spin-torque majority gate (C-STMG) that eliminates the need for carry regeneration, which has been a key limiting factor in conventional C-STMG-based arithmetic circuits. In conventional C-STMG adders, a carry-regeneration block was required to access the carry information generated two stages earlier, resulting in additional power and area overhead. Our proposed structure removes this requirement by enabling direct carry propagation without the carry-regeneration block, thereby reducing device count and energy consumption. To demonstrate the effectiveness and scalability of the proposed design technique, 8-bit, 16-bit, and 32-bit full adders were designed using the carry-regeneration-free C-STMG structure. For the 8-bit implementation, our proposed design reduces dynamic power by 9.68% compared to the conventional C-STMG with carry regeneration. For the 16-bit implementation, the proposed design reduces dynamic power by 9.46% compared to the conventional C-STMG with carry regeneration. A similar reduction trend is observed in the 32-bit full adder (10.02% power reduction), confirming that the structural advantage of eliminating carry regeneration is consistently maintained as the adder bit-width increases. By reducing hardware overhead while preserving the inherent advantages of C-STMGs, the proposed design technique can significantly improve area and energy efficiency. Therefore, our proposed carry-regeneration-free C-STMG architecture provides an effective solution for scalable spintronic arithmetic circuits.