Design and Performance Analysis of CMOS Differential Sense Amplifier for High-Speed DRAM Applications

Abstract—Dynamic Random Access Memory (DRAM) is extensively used in high density memory systems in which thesense amplifier is an essential component to sense and amplify the voltage difference that occurs on the complementary bitlines. In this paper, the design and simulation of the sense amplifier for a DRAM memory is presented, in which the bitline structure is implemented using a differential bit-line structure. The proposed sense amplifier structure uses crosscoupled CMOS transistors, pre-charge and control circuits, and complementary bit lines (BL and BLB) to sense dataeffectively. The circuit design is done and simulated using Cadence Virtuoso to study the transient behavior, powerdissipation, and sensing mechanism of the sense amplifier. The proposed structure provides fast sensing operation with aneffective circuit design.