DESIGN AND IMPLEMENTATION OF CMOS BASED FIR FILTERS

The Finite Impulse Response (FIR) filters are integral components in the digital signal processing system, improving signal quality and reducing unwanted noise levels. Hardware implementation of high-order FIR filters involves intensive arithmetic calculations, which increase chip area, power dissipation, and execution time. Therefore, this work presents a CMOS-based FIR filter implemented in 90 nm technology using Cadence Virtuoso. A Wallace tree multiplier is adopted to accelerate the calculation process, and the structure is compared with existing FIR structures designed using normal array multipliers. The simulation shows that the proposed structure consumes only 27.84 µW of power and offers rapid computation and hardware resource utilization.