Architectural Exploration of Reinforcement Learning and Graph Neural Networks for Gate-Level Logic Synthesis in Modern EDA

This review-style study examines how reinforcement learning agents and graph neural networks are being integrated into gate-level logic synthesis for electronic design automation. It discusses how GNN-derived structural embeddings support pre-layout estimation of signal probability and switching activity, how RL agents explore AIG rewrite trajectories, and why formal equivalence checking must remain a mandatory correctness gate. The work is a derivative study of R. Astillero, "AI-Driven Logic Gate Synthesis and Optimization in Modern Electronic Design Automation (EDA)", Zenodo, 2026, doi:10.5281/zenodo.22703724.