An Adaptive QoS-Aware Arbitration Scheme for Multimaster AHB-to-APB Communication Under Varying Traffic Conditions

This research presents an Adaptive QoS-Aware Arbitration Scheme for Multimaster AHB-to-APB Communication under varying traffic conditions. The proposed approach combines static QoS classification with real-time waiting-time and starvation information to dynamically determine the arbitration priority of multiple bus masters. The arbitration logic is implemented using synthesizable Verilog RTL and integrated with a multimaster AHB-to-APB communication architecture. The design is evaluated in ModelSim under different traffic conditions, ranging from single-master activity to sustained four-master contention. Performance is analyzed using throughput, Jain’s fairness index, average waiting time, and starvation events. Under sustained contention, the proposed scheme achieves a Jain’s fairness index of 0.9992, a throughput of 0.990 grants/cycle, and zero observed starvation events. The work demonstrates the potential of adaptive, QoS-aware arbitration for improving fairness and contention handling in resource-constrained SoC interconnects.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-10-04
DOI
https://doi.org/10.5281/zenodo.23137468
Primary Topic
Interconnection Networks and Systems
Type
preprint
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preprint

An Adaptive QoS-Aware Arbitration Scheme for Multimaster AHB-to-APB Communication Under Varying Traffic Conditions

Khush Shah
Zenodo (CERN European Organization for Nuclear Research)
Interconnection Networks and Systems
preprint

An Adaptive QoS-Aware Arbitration Scheme for Multimaster AHB-to-APB Communication Under Varying Traffic Conditions

Khush Shah
preprint en

Abstract

This research presents an Adaptive QoS-Aware Arbitration Scheme for Multimaster AHB-to-APB Communication under varying traffic conditions. The proposed approach combines static QoS classification with real-time waiting-time and starvation information to dynamically determine the arbitration priority of multiple bus masters. The arbitration logic is implemented using synthesizable Verilog RTL and integrated with a multimaster AHB-to-APB communication architecture. The design is evaluated in ModelSim under different traffic conditions, ranging from single-master activity to sustained four-master contention. Performance is analyzed using throughput, Jain’s fairness index, average waiting time, and starvation events. Under sustained contention, the proposed scheme achieves a Jain’s fairness index of 0.9992, a throughput of 0.990 grants/cycle, and zero observed starvation events. The work demonstrates the potential of adaptive, QoS-aware arbitration for improving fairness and contention handling in resource-constrained SoC interconnects.

Zenodo (CERN European Organization for Nuclear Research)
Dharmsinh Desai University (IN)
Interconnection Networks and Systems
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