Control optimized AES-128 cryptographic architectures achieving 94.2% logic reduction and 50% power savings

The growing deployment of Internet of Things (IoT) devices, embedded systems, and hardware security platforms has increased the demand for lightweight cryptographic architectures capable of delivering strong security under stringent area and power constraints. Although the Advanced Encryption Standard (AES) is widely adopted for secure communication, conventional hardware implementations often incur substantial logic utilization, power consumption, and design complexity, limiting their applicability in resource-constrained environments. This paper presents two control-optimized ultra-compact AES-128 VLSI architectures to improve hardware efficiency while preserving full AES-128 functionality. The proposed designs employ finite state machine (FSM)-based control, iterative datapath reuse, shared functional units, and resource-aware architectural optimization to minimize implementation overhead. Furthermore, the Serial Key-Based AES architecture introduces a shared S-Box structure and a serial-key integration mechanism, eliminating redundant hardware resources and simplifying key management operations. Both architectures were described in VHDL, functionally verified using ModelSim, and synthesized using Quartus II. Experimental results demonstrate that the Serial Key-Based AES architecture requires only 580 logic elements and 441 lookup tables, achieving reductions of up to 94.2% in logic utilization and 95.3% in lookup-table usage compared to a conventional AES implementation. The design operates at a maximum frequency of 135.65 MHz, achieves a throughput of 17.36 Gbps, and reduces power consumption by approximately 50%. The proposed architectures provide an effective balance among security, throughput, area efficiency, and energy consumption, making them well-suited for lightweight cryptography, secure embedded systems, IoT devices, and next-generation VLSI security applications.