High-Pressure Deuterium Annealing Enables Robust Trap Passivation in ALD HfO2/Si MOS Capacitors under High-Temperature Bias Stress

Abstract The continuous scaling down of semiconductor devices has driven the replacement of SiO2-based gate insulators with HfO2 deposited via atomic layer deposition (ALD) to mitigate the leakage current induced by direct tunneling. However, HfO2 thin films deposited via ALD contain process-induced trap states that degrade the device performance, and high-temperature operating conditions owing to device miniaturization further exacerbate trap-related degradation. In this study, high-pressure hydrogen annealing (HPHA) and high-pressure deuterium annealing (HPDA) were applied to HfO2-based metal−oxide−semiconductor (MOS) capacitors for trap passivation, and their electrical characteristics were compared with those of an as-deposited HfO2 MOS capacitor from 30 to 100 °C. HPDA reduced the interface trap density from 1.61 × 1012 eV−1 cm−2 to 1.72 × 1010 eV−1 cm−2 and suppressed the flat-band voltage hysteresis (ΔVFB) to nearly 0 V, showing the best electrical characteristics among the three conditions. Both HPHA and HPDA successfully passivated the interface and bulk trap states within the HfO2 film. Temperature-dependent electrical characteristics revealed that HfO2 annealed with HPHA exhibited a gradual ΔVFB deterioration with increasing measurement temperature, which was attributed to the dissociation of hydrogen-based trap passivation under high-temperature and bias stress. In contrast, HfO2 annealed with HPDA maintained a ΔVFB of nearly 0 V over the entire measurement temperature range, confirming the robust thermal and bias stability of the deuterium-based trap passivation. Furthermore, the suppression of the trap-assisted conduction path through high-pressure annealing demonstrated that HPDA provides the most stable trap passivation in HfO2-based MOS capacitors under high-temperature and high-bias operating conditions.