Mixed-Signal Fractional-N Frequency Synthesis Building Blocks in 45 nm CMOS: Differential DTMOS VCO, Multi-Modulus Divider, and MASH 1-1-1 Controller

This paper presents transistor-level building blocks for fractional-N frequency synthesis in 45 nm CMOS. The main contribution is a five-stage differential current-starved ring VCO using gate-to-body-connected dynamic-threshold MOS devices and sleep-stack transistors placed only in alternate stages to limit the added delay and capacitive loading. The digital section includes an eight-stage multi-modulus frequency divider based on push-pull cascode logic divide-by-2/3 cells and a MASH 1-1-1 sigma-delta controller. All circuits are implemented in Cadence Virtuoso with a nominal 1.0 V supply. Post-layout simulation of the VCO gives an oscillation frequency of 9.24 GHz, phase noise of −124.38 dBc/Hz at a 1 MHz offset, and power consumption of 59.4 µW, corresponding to an FoM of −215.96 dBc/Hz. At Vctrl=0.5 V, the extracted VCO remains oscillatory over 60 combined process, supply voltage, and temperature conditions, with the oscillation frequency ranging from 6.43 to 10.96 GHz. The MMFD, MASH controller, and their integrated fractional-division path are evaluated under the reported nominal operating conditions; PVT robustness of the combined digital path is not established in this work. The digital-path validation includes analysis of fractional-divider command convergence, edge-count consistency, output line spectra, and characterization of the third-order noise-transfer response. The work focuses on the design and validation of individual frequency-synthesis building blocks rather than a complete closed-loop fractional-N PLL.