Machine-Learning-Assisted Mueller–Müller Phase Detection for Robust PAM4 Clock and Data Recovery

High-speed PAM-4 SerDes and wireline interconnects used in data-center, artificial intelligence (AI), high-performance computing (HPC), chip-to-chip, and high-speed networking applications require low-power and hardware-efficient clock and data recovery (CDR) capable of maintaining accurate timing under channel impairments, jitter, and nonlinear phase-detector characteristics. Although the Mueller–Müller phase detector (MMPD) is widely adopted for baud-rate CDR due to its simplicity and robustness, its nonlinear gain characteristic introduces residual timing errors that limit tracking accuracy and increase jitter sensitivity. This work presents a hardware-efficient AI-assisted residual MMPD for baud-rate PAM-4 CDR systems. Instead of replacing the conventional phase detector, a lightweight fully connected neural network learns only the deterministic nonlinear residual correction and generates a compensation term that is added to the classical MMPD output. The proposed residual network employs a compact 1–8–8–1 architecture with ReLU activation, containing only 97 trainable parameters and enabling efficient fixed-point RTL and ASIC implementation. The proposed detector is integrated and evaluated within a complete baud-rate PAM-4 digital CDR comprising a baud-rate sampler, PAM-4 slicer, proportional–integral loop filter, and digitally controlled oscillator, while preserving the stability and low-complexity characteristics of the conventional architecture. Simulation results demonstrate that the proposed detector reduces the phase-detector RMSE from 0.2088 UI to 0.0073 UI, extends the effective linear operating range from approximately ±0.12 UI to ±0.45 UI, and achieves a 13.45% reduction in closed-loop RMS timing error compared with the classical MMPD while maintaining comparable detector noise performance. Owing to its minimal computational overhead, improved detector linearity, compatibility with existing baud-rate CDR architectures, and straightforward hardware realization, the proposed residual-learning framework provides a practical and scalable solution for AI-assisted timing recovery in next-generation high-speed PAM-4 wireline and SerDes receivers.