Hierarchical Architecture-Aware Application Mapping for 3D Network-on-Chip

As the scale of many-core systems-on-chip (SoC) continues to grow, application mapping in Network-on-Chip (NoC) architectures plays a crucial role in determining system-level communication efficiency and overall performance. However, existing mapping approaches often suffer from limited scalability, slow convergence, and unstable solution quality when handling large-scale task graphs with complex communication patterns. To address these challenges, this paper proposes a hierarchical, architecture-aware heuristic optimization framework for NoC application mapping, aiming to achieve scalable, efficient, and robust solutions in large design spaces. Following topology-aware and region-constrained principles, the mapping process is decomposed into three coordinated stages. In the global layout stage, a perturbation-enhanced hierarchical clustering strategy is employed to generate a structurally stable initial mapping aligned with the underlying NoC topology. In the local refinement stage, a unified and problem-oriented optimization scheme is developed based on hash-assisted tabu search, elite archiving, perturbation-enhanced exploration, and adaptive parameter dynamics, enabling accelerated convergence, enhanced search diversity, and improved solution stability. In addition, a convergence control strategy is introduced to adaptively terminate the optimization process when performance improvements become marginal, thereby reducing unnecessary computational overhead. Extensive experiments conducted on real-world benchmarks and large-scale random task graphs demonstrate that the proposed framework consistently outperforms several representative mapping approaches in terms of communication cost, runtime efficiency, communication delay, power and energy consumption, and network throughput. These results confirm the effectiveness and scalability of the proposed framework for NoC-based many-core systems.