Data-Driven Modeling and Circuit-Aware Optimization of Gate-All-Around Multi-Bridge Channel FETs

Aggressive semiconductor scaling toward sub-3 nm technology nodes requires advanced device optimization frameworks capable of efficiently exploring high-dimensional electrostatic design spaces while preserving physics accuracy and circuit-level applicability. Conventional Technology Computer-Aided Design (TCAD) based optimization requires thousands of simulations, limiting scalability for sub-3 nm device design. This work proposes a physics-driven hybrid machine learning and multi-objective evolutionary optimization framework for electrostatic parameter optimization of sub-3 nm Gate-All-Around Multi-Bridge Channel FET (GAA MBCFET) devices targeting ultra-low-power IoT hardware. The framework integrates calibrated TCAD simulation, hybrid surrogate learning using XGBoost and Random Forest, and cellular multi-objective evolutionary optimization to enable fast design exploration under circuit-aware constraints. The hybrid surrogate achieves improved prediction fidelity (RMSE ≈ 0.47, R 2 up to 0.94) while reducing TCAD simulation requirements by ~78% and optimization runtime by ~65%. Device-level optimization achieves subthreshold swing of 57.6 mV/dec, ~22% DIBL reduction, ~40–45% leakage reduction, ~28–32% ON current improvement, and ~30–35% transconductance improvement. Multi-objective optimization improves Pareto hypervolume by ~32–38% with ~35% faster convergence. Circuit-level validation using a sub-3 nm GAA MBCFET SAR ADC demonstrates ~15–22% switching delay reduction and ~35–45% standby power reduction under low-voltage IoT operation. The proposed framework enables physics-consistent, data-driven, and application-aware optimization for next-generation sub-3 nm semiconductor and IoT edge computing platforms.