High-Throughput Phased Decoder with Persistent Candidate Tracking for 50G-PON LDPC Codes

We propose an enhanced phased decoding scheme and the corresponding hardware architecture based on persistent S-min candidate tracking for high-rate low-density parity-check (LDPC) codes of 50G passive optical networks (50G-PON). Conventional phased decoding provides an efficient hardware architecture but cannot reuse updated compressed check-to-variable messages (CCVMs) until the next decoding iteration, resulting in slower decoding convergence. To overcome this limitation, the proposed decoder continuously maintains and updates multiple minimum-value candidates across consecutive phases, enabling newly updated reliability information to be reused without disrupting the regular phased decoding schedule. A corresponding hardware architecture is developed while preserving the fixed-structured wiring network, pipelined processing, and low-complexity characteristics of the phased decoder. The proposed decoder is evaluated through bit error rate (BER) and block error rate (BLER) simulations and implemented on an AMD Kintex UltraScale+ FPGA to assess decoding throughput and hardware resource utilization. Evaluation results show that the proposed decoder reduces the number of clock cycles required to achieve target BER and BLER, improving the throughput of a single decoder module by 21.47% at the cost of additional hardware resources compared with the conventional phased decoder. A frequency-normalized comparison with existing FPGA-based layered decoders further indicates a substantial throughput advantage even after accounting for differences in operating frequency. These results demonstrate that the proposed decoder provides an effective hardware solution for latency-sensitive high-speed 50G-PON receivers.