Topology-Guided Sparse Voltage Measurement Placement for Transient-Voltage Fault-Bus Localization: A Physically Governed Dual-System Evaluation

Sparse voltage measurements make fault-bus localization depend on measurement placement and the physical distinguishability of location labels. We evaluate a deterministic, label-independent topology-guided placement protocol with physically governed localization classes and leakage-resistant condition-level validation on IEEE39 and IEEE123. In the original base protocols, topology-guided CNN1D Top-1 accuracy exceeded the prespecified primary-random layouts by 4.55 and 1.67 percentage points, respectively, although both paired bus-by-condition intervals included zero. In the reviewer-driven 1701-event IEEE39 physical-condition extension, Top-1 was 0.3683 for topology-guided placement and 0.3564 for primary random; the paired difference was +0.0119 with a 95% interval of −0.0493 to 0.0898, which also included zero. Separately, complete enumeration of all 84 feasible IEEE39 k = 3 layouts ranked the topology-guided layout first in Top-1 accuracy, Macro-F1, and mean-hop error under the frozen CNN1D protocol. Load-shift tests produced near-chance Top-1 values, and resistance-shift performance was lower at 20 Ω than at 0.1 Ω. Fixed-capacity, classifier, noise, timing, confusion, and topology-error analyses further bounded the result. The evidence supports reproducible pre-training measurement planning within the tested simulations without establishing statistically certain or universal superiority.

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Journal
Sensors
Published
2026-09-30
DOI
https://doi.org/10.3390/s26196203
Primary Topic
VLSI and Analog Circuit Testing
Type
article
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Topology-Guided Sparse Voltage Measurement Placement for Transient-Voltage Fault-Bus Localization: A Physically Governed Dual-System Evaluation

Yu Xu, Jisheng Xing, Zhankun Wang
Sensors
VLSI and Analog Circuit Testing
article

Topology-Guided Sparse Voltage Measurement Placement for Transient-Voltage Fault-Bus Localization: A Physically Governed Dual-System Evaluation

Yu Xu, Jisheng Xing, Zhankun Wang
article en

Abstract

Sparse voltage measurements make fault-bus localization depend on measurement placement and the physical distinguishability of location labels. We evaluate a deterministic, label-independent topology-guided placement protocol with physically governed localization classes and leakage-resistant condition-level validation on IEEE39 and IEEE123. In the original base protocols, topology-guided CNN1D Top-1 accuracy exceeded the prespecified primary-random layouts by 4.55 and 1.67 percentage points, respectively, although both paired bus-by-condition intervals included zero. In the reviewer-driven 1701-event IEEE39 physical-condition extension, Top-1 was 0.3683 for topology-guided placement and 0.3564 for primary random; the paired difference was +0.0119 with a 95% interval of −0.0493 to 0.0898, which also included zero. Separately, complete enumeration of all 84 feasible IEEE39 k = 3 layouts ranked the topology-guided layout first in Top-1 accuracy, Macro-F1, and mean-hop error under the frozen CNN1D protocol. Load-shift tests produced near-chance Top-1 values, and resistance-shift performance was lower at 20 Ω than at 0.1 Ω. Fixed-capacity, classifier, noise, timing, confusion, and topology-error analyses further bounded the result. The evidence supports reproducible pre-training measurement planning within the tested simulations without establishing statistically certain or universal superiority.

SensorsVol. 26(19)
Beihua University (CN)
Openalex Percentile: Top 6%
VLSI and Analog Circuit Testing
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Topology-Guided Sparse Voltage Measurement Placement for Transient-Voltage Fault-Bus Localization: A Physically Governed Dual-System Evaluation — Yu Xu, Jisheng Xing, et al. · Sensors (2026) | TGRS Research Map | TGRS