HAR-ASIC: A Configurable Edge-AI Human Activity Recognition Circuit for Ultra-Low Power Wearable Devices

We present an application-specific integrated circuit (ASIC) using digital hardware design to maximise energy-efficiency of human activity recognition (HAR) in autonomous wearable devices. The HAR-ASIC was designed in 22 nm technology and includes a battery of configurable, hardware-optimised feature extraction functions along with a decision tree ensemble classifier, thus serving as an edge AI device for local sensor data processing. We validate the HAR-ASIC based on post-layout process data with five HAR datasets and show the design scalability for configurations to maximise energy saving and others to maximise recognition performance. We show that feature extraction often requires up to 100 times more energy than the classification function. Our configuration analysis shows that feature extraction energy consumption can be reduced by factors of two to five, with at most 3% loss in F1-score, depending on the dataset. Across all datasets, feature extraction and classification energy was between 64 and 678 nJ per inference for Pareto-optimal configurations using sliding window buffers of up to 512 samples. We conclude that the highly configurable HAR-ASIC design could be the basis to realise ultra-low power sensor-edge AI systems for continuous wearable HAR and possibly further edge AI applications.