Physics-Informed Neural Networks on Analog In-Memory Computing Hardware: A Systematic Validation with IBM's Calibrated IMC Simulator

Physics-Informed Neural Networks (PINNs) embed governing equations in the training loss and are attractive for edge deployment, while analog In-Memory Computing (IMC) offers order-of-magnitude energy-efficiency gains for neural-network inference. This paper presents a systematic validation of PINN robustness on analog IMC hardware using IBM’s calibrated Analog Hardware Acceleration Kit (aihwkit), which models non-idealities measured on real phase-change memory (PCM) and ReRAM devices. Clean FP32 networks trained with the exact protocol of a prior simulation study are deployed through two hardware models: (i) a direct analog of the study’s custom quantization-plus-Gaussian-noise layer, and (ii) the full IBM inference flow comprising programming noise, power-law conductance drift, 1/f and RTS read noise, drift compensation, and per-layer-ranged DAC/ADC periphery. Across two benchmarks (damped oscillator ODE and 1D heat PDE) and five random seeds, PINNs cut oscillator extrapolation error by 94.8–96.7% relative to standard networks at 4–8-bit weight precision, while the heat-equation improvement reaches 73.3% at 4-bit and 95.0% at 8-bit. PINNs keep the extrapolation-to-interpolation degradation ratio at 1.1–2.5× versus 21–112× for standard networks, and maintain a 96.3–96.4% advantage over standard networks across a simulated 11.6-day PCM aging interval with standard drift compensation. The advantage transfers to a calibrated ReRAM device model (90.2–94.1%), while realistic 7-bit DAC / 9-bit ADC peripheral quantization produces no measurable degradation. A mixed-precision adaptive variant (AdaPINN) remains robust where the standard PINN degrades under extreme 4-bit ADC stress. Noise-aware training is confirmed counterproductive for PINNs, producing a 3.6× higher extrapolation MSE than clean training and replicating the prior result to three decimal places. We further identify a deployment constraint absent from FP32 evaluation: the un-normalized PINN input exceeds default IMC input/output ranges and collapses under a 2-bit DAC, making input normalization a first-class co-design decision

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-09-30
DOI
https://doi.org/10.5281/zenodo.23054274
Primary Topic
Advanced Memory and Neural Computing
Type
preprint
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Physics-Informed Neural Networks on Analog In-Memory Computing Hardware: A Systematic Validation with IBM's Calibrated IMC Simulator

Harish K
Zenodo (CERN European Organization for Nuclear Research)
Advanced Memory and Neural Computing
preprint

Physics-Informed Neural Networks on Analog In-Memory Computing Hardware: A Systematic Validation with IBM's Calibrated IMC Simulator

Harish K
preprint en

Abstract

Physics-Informed Neural Networks (PINNs) embed governing equations in the training loss and are attractive for edge deployment, while analog In-Memory Computing (IMC) offers order-of-magnitude energy-efficiency gains for neural-network inference. This paper presents a systematic validation of PINN robustness on analog IMC hardware using IBM’s calibrated Analog Hardware Acceleration Kit (aihwkit), which models non-idealities measured on real phase-change memory (PCM) and ReRAM devices. Clean FP32 networks trained with the exact protocol of a prior simulation study are deployed through two hardware models: (i) a direct analog of the study’s custom quantization-plus-Gaussian-noise layer, and (ii) the full IBM inference flow comprising programming noise, power-law conductance drift, 1/f and RTS read noise, drift compensation, and per-layer-ranged DAC/ADC periphery. Across two benchmarks (damped oscillator ODE and 1D heat PDE) and five random seeds, PINNs cut oscillator extrapolation error by 94.8–96.7% relative to standard networks at 4–8-bit weight precision, while the heat-equation improvement reaches 73.3% at 4-bit and 95.0% at 8-bit. PINNs keep the extrapolation-to-interpolation degradation ratio at 1.1–2.5× versus 21–112× for standard networks, and maintain a 96.3–96.4% advantage over standard networks across a simulated 11.6-day PCM aging interval with standard drift compensation. The advantage transfers to a calibrated ReRAM device model (90.2–94.1%), while realistic 7-bit DAC / 9-bit ADC peripheral quantization produces no measurable degradation. A mixed-precision adaptive variant (AdaPINN) remains robust where the standard PINN degrades under extreme 4-bit ADC stress. Noise-aware training is confirmed counterproductive for PINNs, producing a 3.6× higher extrapolation MSE than clean training and replicating the prior result to three decimal places. We further identify a deployment constraint absent from FP32 evaluation: the un-normalized PINN input exceeds default IMC input/output ranges and collapses under a 2-bit DAC, making input normalization a first-class co-design decision

Zenodo (CERN European Organization for Nuclear Research)
Amrita Vishwa Vidyapeetham (IN)
Affordable and clean energy
Advanced Memory and Neural Computing
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Physics-Informed Neural Networks on Analog In-Memory Computing Hardware: A Systematic Validation with IBM's Calibrated IMC Simulator — Harish K · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS