An Efficient Virtual Channel Power-Gating Method using Dynamic Bypass in NoC Routers

With transistor sizes continuing to reduce, static power consumption has gradually become a major part of the overall power consumption of Network-on-chip (NoC). Therefore, many power gating methods have been proposed to reduce the increasing static power consumption. However, conventional power gating techniques introduce new problems such as high latency, low scalability and network disconnection. To address these issues, in this paper, we propose an efficient virtual channel (VC) power gating method using dynamic bypass. Firstly, each port of the router dynamically powers on and off the VC buffers based on network traffic, thus reducing the static power consumption of the router. Secondly, a straight bypass is created on each port to handle straight packets and a dynamic bypass shared by all ports is used to handle other types of packets. The bypass mechanism facilitates packet ejection, transmission, and injection operations even when the VC buffer is deactivated, effectively reducing packet latency and enhancing router performance through optimized data flow management. Finally, the experimental results show that the proposed power gating method reduces the static power consumption by 84.5% and packet latency by 8.4% on average compared to the baseline router, while increasing the area overhead by 13.29%.