Can a photonic state-space model be trained on-chip? A pre-registered in-situ-training bake-off on a realistic silicon-nitride ring substrate

Can the physical recurrence of a dissipative photonic state-space model be trained on-device? We study this question in simulation using a pre-registered silicon-nitride coupled-ring substrate with finite Q, saturating gain, and amplifier noise. Physics-aware training (PAT) and model-free SPSA reach the registered margin of an exact-gradient ceiling on all eight seeds; PAT requires 4.6 times fewer device passes. Hamiltonian-echo learning fails its feasibility gate because dissipation defeats the echo. A single input drive reaches approximately three of 32 rings, whereas four taps recover controllability across all 32; the deployed equalizer nevertheless uses only six to eight rings. Against offline calibration, deployment, and readout retraining, a corrected sweep shows no resolved difference at five calibration-error levels spanning 5-30%. Under independent per-ring drift, PAT clears a frozen 2-fold advantage rule with a 2.42-fold median SER ratio; the ratio's own 95% interval is [1.7, 4.6]. Common-mode drift does not clear the rule. A registered prediction that the damping optimum follows task memory span fails. An inline systems follow-up also fails its energy gate: at 0.1-2 GS/s, even the most favorable digital/photonic energy ratio is 0.64 against a per-tap digital equalizer. Total training energy remains unmeasured; optical duration alone is not wall time. The results establish simulated trainability and its limits, without claiming a hardware demonstration or an energy advantage. Code, registrations, and the correction audit trail accompany the paper. This is an unreviewed simulation preprint. The accompanying source ZIP contains scientific supplementary notes, figures, pre-registration records, the correction audit trail, and archived numerical results. The title poses the hardware question; this deposit reports simulation, not on-chip experimental training. Simulation code, analysis and manuscript drafts were produced with extensive assistance from AI coding agents (Anthropic's Claude, via Claude Code) under the author's direction; review-independence conditions are described in section 8.4.

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-09-29
DOI
https://doi.org/10.5281/zenodo.23041523
Primary Topic
Neural Networks and Reservoir Computing
Type
preprint
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preprint

Can a photonic state-space model be trained on-chip? A pre-registered in-situ-training bake-off on a realistic silicon-nitride ring substrate

Lucas Talandier
Zenodo (CERN European Organization for Nuclear Research)
Neural Networks and Reservoir Computing
preprint

Can a photonic state-space model be trained on-chip? A pre-registered in-situ-training bake-off on a realistic silicon-nitride ring substrate

Lucas Talandier
preprint en

Abstract

Can the physical recurrence of a dissipative photonic state-space model be trained on-device? We study this question in simulation using a pre-registered silicon-nitride coupled-ring substrate with finite Q, saturating gain, and amplifier noise. Physics-aware training (PAT) and model-free SPSA reach the registered margin of an exact-gradient ceiling on all eight seeds; PAT requires 4.6 times fewer device passes. Hamiltonian-echo learning fails its feasibility gate because dissipation defeats the echo. A single input drive reaches approximately three of 32 rings, whereas four taps recover controllability across all 32; the deployed equalizer nevertheless uses only six to eight rings. Against offline calibration, deployment, and readout retraining, a corrected sweep shows no resolved difference at five calibration-error levels spanning 5-30%. Under independent per-ring drift, PAT clears a frozen 2-fold advantage rule with a 2.42-fold median SER ratio; the ratio's own 95% interval is [1.7, 4.6]. Common-mode drift does not clear the rule. A registered prediction that the damping optimum follows task memory span fails. An inline systems follow-up also fails its energy gate: at 0.1-2 GS/s, even the most favorable digital/photonic energy ratio is 0.64 against a per-tap digital equalizer. Total training energy remains unmeasured; optical duration alone is not wall time. The results establish simulated trainability and its limits, without claiming a hardware demonstration or an energy advantage. Code, registrations, and the correction audit trail accompany the paper. This is an unreviewed simulation preprint. The accompanying source ZIP contains scientific supplementary notes, figures, pre-registration records, the correction audit trail, and archived numerical results. The title poses the hardware question; this deposit reports simulation, not on-chip experimental training. Simulation code, analysis and manuscript drafts were produced with extensive assistance from AI coding agents (Anthropic's Claude, via Claude Code) under the author's direction; review-independence conditions are described in section 8.4.

Zenodo (CERN European Organization for Nuclear Research)
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Neural Networks and Reservoir Computing
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Can a photonic state-space model be trained on-chip? A pre-registered in-situ-training bake-off on a realistic silicon-nitride ring substrate — Lucas Talandier · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS