Ultralow‐Energy Analog Reservoir Computing via Reconfigurable 2‐Transistor Memory

ABSTRACT Reservoir computing (RC) offers a promising route to real‐time temporal information processing and is widely regarded as an energy‐efficient alternative to conventional von Neumann architectures. Paradoxically, many hardware RC systems have yet to demonstrate clear advantages in both array‐level energy efficiency and processing speed, despite these being among the field's central motivations. Furthermore, their practical viability is limited by structural complexity and insufficient robustness. Here, we report a reconfigurable, dynamic random‐access memory (DRAM)‐like physical RC platform based on an oxide channel two‐transistor (2T) cell, providing a practical route toward low‐energy, fast, robust, and structurally simple physical RC. Within a single device footprint and fabrication flow, the same 2T cell can be reconfigured to volatile reservoir dynamics or quasi‐non‐volatile readout memory. Its operating mode is selected by the hold bias, enabling electrical reconfiguration with tunable relaxation dynamics. This compact strategy enables spatiotemporal programmability while preserving process simplicity, as validated by motion‐detection simulations. Owing to multi‐V hold spatiotemporal encoding, the proposed RC architecture achieves a 3.98‐fold reduction in device‐array‐level read energy and requires 8.00‐fold fewer trainable synaptic weights than the ANN baseline. These results position oxide 2T memory as a strong candidate for next‐generation non‐von‐Neumann artificial intelligence (AI) hardware.