Edge Electrostatic Inhomogeneity Correlates with Hysteresis and Localized Charging in Lithographically Defined Graphene Nanoribbon Devices

Abstract Lithographically defined graphene nanoribbons (GNRs) are attractive for graphene nanoelectronics and single-electron devices, but their performance is often limited by edge roughness, polymer residues, adsorbates, and graphene/SiO2 interfacial traps introduced during top-down processing. Here, we correlate process-defined edge disorder with local electrostatic inhomogeneity and transport stability in geometry-matched GNR devices containing a fixed central graphene island and 150, 100, or 50 nm constrictions. Smooth and rough edge classes, with representative edge roughnesses of ≈3 and ≈15 nm, respectively, are characterized by AFM, TEM, Raman spectroscopy, Kelvin probe force microscopy (KPFM), and temperature-dependent electrical transport. Controlled KPFM measurements, including dry-N2 controls, show that rough ribbons exhibit larger edge–basal contact-potential contrast and stronger along-edge potential fluctuations than smooth ribbons, consistent with enhanced edge-localized electrostatic disorder. These electrostatic differences correlate with broader gate-sweep hysteresis, lower transport stability, and larger effective trap signatures. Low-temperature bias spectroscopy further shows that smooth 50 nm devices exhibit cleaner localized-charging features with effective addition-energy scales up to ≈128 meV, whereas rough 50 nm devices show irregular disorder-dominated blockade features consistent with coupled puddles or multiple localized islands and a lower effective blockade energy scale of ≈4.3 meV. Across the width series, normalized roughness organizes systematic trends in mobility, on/off ratio, hysteresis, and electrostatic contrast, linking process-defined edge morphology to device-level transport response. These results establish a proof-of-concept correlation in which KPFM-derived edge electrostatic inhomogeneity, reflecting the combined process-defined edge/near-edge environment, tracks gate-sweep hysteresis and low-temperature charging behavior, identifying it as a candidate pre-cryogenic screening descriptor for lithographically patterned GNR devices and motivating validation on larger device cohorts.