An Efficient Binary-Field ECC Hardware Design for an SM2-Style Digital Signature Flow

We present a binary-field ECC hardware benchmark for an SM2-style signing flow, rather than a standard-compliant implementation of the 256-bit prime-field SM2 parameters. The design uses the NIST K-233 curve over GF(2233), a Karatsuba multiplier, and a Montgomery ladder in López–Dahab projective coordinates. Parallel scheduling reduces the point-addition and point-doubling critical paths from 4M+S+2A and 2M+3S+A to 2M+S+2A and M+2S+A. Implemented on a Virtex-7 VC707 at 300 MHz, the standalone point-multiplication core uses 32,720 LUTs and 46,830 flip-flops and completes its start-to-done operation in 14,704 cycles (49.01 μs); the corresponding signing and verification measurements are 16,364 cycles (54.55 μs) and 31,049 cycles (103.50 μs), respectively. We additionally evaluate a dual-nonce defense against a controlled nonce-register fault and lattice attack. For l=6 leaked bits and w=51–70 signatures per recovery campaign, the unprotected and point-validation designs approach complete recovery as w increases, whereas the dual-nonce design maintains an approximately 2% recovery rate across the tested range. The countermeasure adds 0.30% LUTs, 0.09% flip-flops, and 1.22% signing time.