Designing an Interactive Verilog Practice Tool for Computer Engineering Students

Students learning Digital Logic Design may understand how a circuit should work but still find it difficult to write and check thecorresponding Verilog code. This paper presents a prototype practice tool designed to help students work through beginner logic-gateexercises. The prototype includes 11 lessons, a practice area where users can choose a gate and number of inputs, and a dashboard thattracks exercise attempts and completion. The practice area generates a truth table and starter Verilog code based on the user’sselections. The planned evaluation will examine students’ performance before and after using the tool and gather feedback.