Post-Layout Symmetry and Trade-Offs in a CMOS Hysteresis Comparator

Analog layouts often use matched devices to reduce sensitivity to process gradients. However, the resulting interconnect can introduce parasitic coupling. We compare four DRC-clean, LVS-equivalent layouts of the same hysteresis comparator, implemented in a 130 nm bulk CMOS process with 5 V, thick-oxide devices. The schematic, bias, load, and R+C+CC extraction flow are held fixed, while placement and routing vary together. At 5.0 V and 25 °C, the strictly common-centroid layout has a simulated 315.758 mV high-state output ripple despite nearly balanced input capacitances. Among the protected layouts, C3 yields the narrowest finite-slew switching window, whereas C4 reduces nominal ripple to 0.275 mV. In 200 mismatch samples at the nominal 5.0 V supply, C3 and C4 have similar threshold dispersion, while C4 retains lower output ripple. The observations support evaluating placement and routing together with device matching. The preferred layout depends on the chosen performance metric.