New efficient CMOS binary-to-optimum Double-Base Encoder

Present effort discloses a novel three‑step design-strategy to encode the binary-input into its optimised Double-Base identical and the related circuit-topology is divulged. The idea is demonstrated by comparing and dividing the binary-input with ‘0110’(i.e.‘6’) and applying proposed hardware-optimisation using k-map. A 4-bit Binary-to-Optimum Double-Base Encoder (B-ODE) is designed and laid-out using Berkeley SIM-4 parameters on TSMC32nm C-MOS technology-node with 0.9-Volt main-supply at room temperature. The worst-case post-layout power-delay characteristic of proposed B-ODE with 1fF to 10fF load is included. The robustness against possible PVT (Process-Voltage-Temperature)-variations with 1 fF load, ±10%-supply and ±3σ-process variation from nominal at −40°C to 85°C is investigated. Study shows that the proposed 4-bit B-ODE can reduce PDP by 67.39% compared to the most recent competitive strategy in open literature. Finally, the 4-bit B-ODE is extended to explore 8-bit B-ODE exploiting scalability to deal with larger-input.