Adversarial Robustness of Time-Rotation Architectures: Conditional Advantages and Failure Boundaries

English translation of the Chinese paper (Chinese version: Zenodo DOI 10.5281/zenodo.23010108). Professional complete English version; all experimental values and terminology preserved.

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-09-28
DOI
https://doi.org/10.5281/zenodo.23009846
Primary Topic
VLSI and Analog Circuit Testing
Type
preprint
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preprint

Adversarial Robustness of Time-Rotation Architectures: Conditional Advantages and Failure Boundaries

Jinhu Zhang
Zenodo (CERN European Organization for Nuclear Research)
VLSI and Analog Circuit Testing
preprint

Adversarial Robustness of Time-Rotation Architectures: Conditional Advantages and Failure Boundaries

Jinhu Zhang
preprint en

Abstract

English translation of the Chinese paper (Chinese version: Zenodo DOI 10.5281/zenodo.23010108). Professional complete English version; all experimental values and terminology preserved.

Zenodo (CERN European Organization for Nuclear Research)
VLSI and Analog Circuit Testing
DOIOpen Access PDFOpenAlex
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Adversarial Robustness of Time-Rotation Architectures: Conditional Advantages and Failure Boundaries — Jinhu Zhang · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS