Automated Identification of Error-Tolerant Convolutional Neural Network Layers for Approximate Logic Synthesis

Modern artificial intelligence (AI) and integrated circuit technologies face severe energy constraints and thermal design power (TDP) limits. To address this challenge, this paper explores an automated framework combining deep neural network criticality analysis with AI-driven approximate logic synthesis. By systematically evaluating error tolerance in Convolutional Neural Network (CNN) layers and deploying custom approximate hardware blocks—such as the New Approximate Adder (NAA)—the proposed approach achieves up to a 57% reduction in power-delay product while strictly preserving AI classification accuracy. Ultimately, this software-hardware integration provides a scalable blueprint for designing energy-efficient microchips for sustainable AI deployment.