Imprint‐Controlled Tuning of Memory Windows in Ferroelectric Nonvolatile Memory Field‐Effect Transistors With Asymmetric Multilayers

ABSTRACT Optimizing the memory characteristics of 2D ferroelectric nonvolatile memory field‐effect transistors (NVMFETs) remains challenging because interface‐trapped charges and fixed charges often induce threshold‐voltage instability and degrade device performance. Here, we demonstrate that ferroelectric imprint engineering in BaTiO 3 /PbTiO 3 (BTO/PTO) multilayer gate dielectrics provides a means of systematically tuning the electrical distinguishability of memory states in NVMFETs employing single‐layer graphene and monolayer MoS 2 channels. By varying the BTO/PTO thickness ratio, the imprint strength was systematically tuned through asymmetric shifts of the ferroelectric hysteresis loops. Interestingly, the dependence of the current‐state separation on imprint strength varied with the channel material. While graphene‐based devices exhibited a monotonic increase in current‐state separation with increasing imprint strength, MoS 2 ‐based devices showed a maximum current‐state separation at an intermediate imprint strength, reflecting the interplay between imprint‐induced polarization modulation and channel carrier transport. These results indicate that engineered ferroelectric imprint can serve as a device‐engineering parameter for tailoring the electrical distinguishability of memory states in 2D ferroelectric NVMFETs, providing guidance for channel‐specific optimization of nonvolatile memory devices.