Logic Topology-Based Scan Compression Optimization for Large-Scale Hierarchical DFT

Scan compression technology, as the most effective test structure, is widely applied in scan chain-based Design for Testability (DFT). However, with the continuous increase in chip scale, the diversity of full-chip functional modules necessitates reliance on Automatic Test Pattern Generation (ATPG) analysis of entire netlists to obtain optimal compression solutions. This severely constrains chip development speed and becomes a critical challenge. This paper proposes a logic topology-based scan compression analysis method that significantly reduces or even eliminates full-flow iterations. Its innovation lies in: analyzing the compression characteristics of EDT (Embedded Deterministic Test), and utilizing the logical topology of working modules to obtain logic cones that constrain deterministic information. By analyzing the test vector distribution resulting from deterministic and random factors, it constructs a compression performance evaluation, thereby avoiding iterations. Based on practical industrial applications and under the premise of a low-power control scheme, this paper proposes an integrated optimization solution based on test channels. This method balances test-channel usage, test time, and test-data capacity for the evaluated industrial modules. Compared with the actual EDT ATPG results, the estimated compression ratios exhibit a mean absolute percentage error of approximately 3.23%, while the maximum module-level relative error is approximately 16.71%. The proposed static estimation flow reduces the number of full ATPG optimization iterations and, for the evaluated design flow, reduces EDA processing time by over 90%. Furthermore, relative to the unified compression-ratio scheme, the balanced configuration reduces normalized channel demand by 75%, test-data volume by 43%, and test time by 47%.