The ePIC-dRICH RDO: an FPGA-based card for a photodetection integrated system

The dRICH detector is part of the ePIC-PID system and includes more than 300 thousand SiPMs, used as photosensors for the Cherenkov light produced by aerogel and C$_2$F$_6$ gas. The dRICH is segmented in 1248 PDUs, including both sensors and readout electronics. The PDU provides 4 front-end boards, integrating each an ALCOR64 ASIC paired to a 64-SiPM matrix and designed to produce timestamps with 40 ps LSB resolution. The RDO card is included inside the PDU and is an FPGA-based card that acts as concentrator for the ALCOR data, pre-processed and sent to the back-end system using a streaming readout architecture.The RDO card is designed to meet several key requirements: compact layout, low power consumption, reliable communication under radiation exposure, and high data throughput. The card must fit inside the PDU of $5 \times 5 \times 14$ cm$^3$ in size. The components were selected to sustain high data-rate ($\sim$6 Gb/s) generated by the ALCOR TDC electronics, largely driven by the SiPM Dark Count Rate (DCR) that can reach up to 300 kHz/ch. Since in the dRICH electronics region a maximum instantaneous flux $\phi _5 (h>20\text{ MeV}) \approx 700 \text{ Hz/cm}^2$ and a TID$_5$ $\approx$ 2.3 krad are estimated considering a five safety factor, each component was tested for TID sensitivity and SEU mitigation strategies are being implemented. The RDO core is an AU15P SRAM-based FPGA from AMD, responsible for PDU control and high-speed readout of differential data lines from the 4 ALCOR ASICs. To mitigate SEU occurrence on the AU15P Configuration RAM, a Microchip MPF050T FLASH-based FPGA, together with a Micron Technology MT25QU01 FLASH memory, implements blind-scrubbing procedure via a dedicated bus. This approach has been validated during irradiation campaigns. Data transmission to the back-end is handled by a CERN VTRx+ radiation-hard optical transceiver, directly connected to the AU15P FPGA and providing a 10 Gb/s uplink. Two jitter-attenuating clock multipliers (Si5326 and Si5319, Skyworks Solutions) serve as main PLL systems. The Si5319 generates the reference clock for the AU15P transceiver, while the Si5326 is used to clean the AU15P reconstructed clock (78.8 MHz) and provides the 394 MHz clock for the ALCOR ASICs. Performance obtained on reconstructed clock jitter will be reported.The power network design includes two low noise LTM4709 LDO-circuits (Linear Technology) and a Microchip ATtiny417 microcontroller ($\mu$C), which will be substituted by the Microchip SAMD21 $\mu$C as it showed higher radiation tolerance. The first ten RDO cards were successfully validated in laboratory conditions and then deployed as the back-bone for the DAQ system of the dRICH-prototype, reading 8 PDUs. A preliminary readout based on IPbus protocol over a 1 Gb/s Ethernet link was used. Each RDO was connected externally to a prototype-PDU via FireFly cable adapters. The prototype-PDU integrates eight ALCOR32 ASICs, each designed for 32-channel SiPM readout. The system demonstrated stable performance up to approximately 30 kHz DCR, due to the IPbus limitation. The next steps towards full design validation, firmware architecture and link protocols, under evaluation for final implementation, will be discussed.