Deterministic Foreground Calibration of Gain and Integral Nonlinearity in Constant-Slope Digital-to-Time Converters for Fractional Output Dividers

Fractional output dividers (FODs) derive many clock domains from one integer-N phase-locked loop, but the gain error and integral nonlinearity (INL) of their digital-to-time converter (DTC) limit spectral purity. Existing FOD calibrations estimate the INL statistically, with no deterministic step count or residual bound. This paper presents a deterministic foreground calibration that measures the DTC bit weights in the delay domain. Reconfiguring an R-2R ladder bit by bit inside a constant-slope DTC maps each weight to a SAR-driven edge comparison against a replica chain, so the five mismatch-dominant weights are extracted inside a fixed 124-decision sequence and corrected through a 32-entry look-up table. Allocating one input period to discharge and N−1 periods to DAC settling enables a 10 GHz input. Exact conditions are derived for gain measurement, offset–gain convergence, and weight extraction, together with the smooth curvature that per-bit calibration cannot observe. Transistor-level simulations in 22 nm FDSOI show chain tracking of 0.94 and offset–gain convergence below half the 12.2 fs calibration step. A 200-die system-level Monte Carlo anchored to these statistics reduces the median peak INL from 4.1 to 0.32 LSB (24.4 fs LSB) and the worst fractional spur from −75.5 dBc to the −91 dBc quantization floor after 0.59 ms of calibration; the resulting 28 fs rms edge jitter permits 95 dB aperture-limited SNDR in a sampled sensor front end at 100 MHz.