AI-Augmented Logic Synthesis for Edge-Deployed Swimmer Detection Systems

Vision-based swimmer and drowning detection systems, built primarily on lightweight YOLO architectures, have achieved measurable gains in accuracy while shrinking model size for resource-constrained edge hardware. However, Field-Programmable Gate Array (FPGA) accelerators hosting these models continue to rely on conventional logic synthesis, leaving a hardware-level optimization layer unaddressed even as pool and beach terminals remain constrained by strict power budgets. This paper proposes a conceptual framework applying AI-driven logic synthesis, specifically Reinforcement Learning-based And-Inverter Graph rewriting, Graph Neural Network-based Power-Performance-Area (PPA) prediction, and Large Circuit Model-based translation, to swimmer detection accelerator design. The framework maps each methodology to specific design stages, incorporates domain-specific constraints like safety-critical verification and outdoor power budgets, and compares them against practices in existing FPGA-based implementations. The analysis indicates current accelerator optimization concentrates entirely at the model level, identifying gate-level synthesis as an unexplored opportunity for power and area efficiency requiring future empirical validation.