A Wideband Fractional-N PLL with Transition-Detection DAC for SDM-Based Quantization Noise Cancellation in Precision Timing Measurement

This article presents a fractional-N PLL employing a first-order sigma–delta modulator (SDM) and a transition-detection digital-to-analog converter (TD-DAC) to reduce transition-related quantization-induced phase disturbances. The proposed TD-DAC selectively injects a compensation current in response to sign transitions in the SDM error sequence, enabling localized phase correction without requiring high-resolution or continuously operating digital-analog converter (DAC) circuitry. To accommodate a wide tuning range, the proposed PLL integrates an extended-range multi-modulus divider (MMD) supporting division ratios from 4 to 2047. Fabricated in a 110-nm CMOS process, the PLL occupies an active area of 0.284 mm2 and operates from dual supply voltages of 1.5 V and 3.3 V. The synthesized frequency covers a 0.4-to-1.7-GHz range. Measurement results demonstrate an integrated RMS jitter of 3.78 psrms over a 100-Hz-to-40-MHz integration bandwidth, with a time-domain jitter of 3.52 psrms and 22.1 pspp, while consuming a total power of 21.2 mW from 1.5-V/3.3-V dual supplies at 1.6125-GHz.