A Novel Schematic–Layout Co-Analysis Framework for Selective Radiation Hardening in Nanoscale Technology

Abstract Technology scaling in nanoscale FinFET technologies increases circuit susceptibility to radiation-induced single event effects (SEEs). This work proposes a schematic–layout co-analysis and selective hardening framework for radiation-aware circuit design. The methodology combines LET-based fault injection at the schematic level with three-dimensional layout-aware particle strike simulation to identify the most vulnerable nodes and their corresponding sensitive physical regions. Guided by this analysis, selective hardening strategies are applied to improve radiation resilience with minimal overhead. The framework is validated on three representative circuits implemented in FreePDK15 technology: a 2:1 MUX, a multi-supply level shifter, and a D flip-flop. Experimental results show that the proposed approach increases the minimum $$LET_{\textrm{th}}$$ of the Multiplexer (MUX), level shifter, and D-Flip-Flop (DFF) by $$38\mathrm {MeV\cdot cm^2/mg}$$ , $$18\mathrm {MeV\cdot cm^2/mg}$$ , and $$12\mathrm {MeV\cdot cm^2/mg}$$ , respectively. In addition, the hardened designs reduce the SET cross-section for all the case studies, especially, by nearly one order of magnitude for the level shifter, while maintaining moderate implementation overhead. These results demonstrate the effectiveness of the proposed framework for overhead-efficient radiation-aware design in advanced FinFET circuits.