Temperature and trap charge sensitivity analysis of a Si-Ge heterojunction dual stack source raised drain tunnel FET

This work investigates the impact of interface trap charges (ITCs) and temperature on the DC and RF/analog performance of a dual-stack source raised-drain tunnel field-effect transistor (DSSRD-TFET). The device uses a silicon–germanium source stack and raised-drain architecture to improve electrostatic control, enhance tunneling efficiency, and suppress leakage. Negative interface trap charges (NITC), zero interface trap charges (ZITC), and positive interface trap charge (PITC) conditions are analyzed using Sentaurus TCAD from 200 to 400 K. PITC increases the ON-state current (I On ) by strengthening the tunneling-junction electric field and enhancing carrier accumulation but simultaneously reducing the subthreshold steepness, leading to a higher subthreshold swing (SS). In contrast, NITC suppresses I On but provides better subthreshold control, resulting in lower SS. At 300 K, the DSSRD-TFET achieves an I On of 1.12 × 10 –4 A/µm, an OFF-state current (I Off ) of 1.55 × 10 –18 A/µm, and an I On /I Off ratio of 7.27 × 10 13 under PITC. Temperature-dependent simulations show that PITC maintains the strongest RF/analog response across the studied temperature range.