Hardware Integrity Verification Through Forensic Reasoning Using Manufacturing Images

Modern electronic assembly relies on complex global supply chains, making verification of component authenticity and consistency with the intended design increasingly important. Existing automated inspection approaches typically formulate this as classification or anomaly detection, providing limited insight into the physical evidence behind their conclusions and often failing to distinguish expected manufacturing variation from hardware integrity events. This paper presents a scenario-based method that formulates component verification as an evidence-based reasoning process. Semantic observations and learned visual evidence extracted from standard manufacturing images are evaluated against expected observations for candidate scenarios, including normal production evolution, approved AVL substitutions, unexpected component changes, and counterfeit-related events. The method was developed using more than 6.5 billion component images from high-volume SMT manufacturing. Quantitative evaluation across five controlled dual-population datasets comprising 1001 samples achieved 97.45% evidence-discrimination accuracy for manufacturing changes involving MPN, manufacturer, and production site. In a separate ground-truthed experiment, 19 of 20 counterfeit components were correctly detected within 200 components, with one false positive, corresponding to 99.0% accuracy. Longitudinal analysis of 429.6 million inspected components across 15 active EMS sites showed distinct behavior of marking-content changes: marking-to-MPN mismatches decreased by approximately 95% from 2023 to 2026 YTD, whereas date-code mismatches remained comparatively stable, illustrating how different changes within the same marking support different manufacturing scenarios and operational responses. The results demonstrate how visual and semantic evidence can jointly distinguish legitimate manufacturing variation, component substitutions requiring verification, and counterfeit-related inconsistencies. The methodology provides a scalable basis for component-level hardware assurance while creating a traceable digital record of the physical evidence supporting each assessment.