A Collaborative Optimization Method for Area and Power Consumption of FPRM Logic Circuits Based on an Experience Interaction Mechanism
To address the low quality of Pareto solution sets and poor search efficiency in multi-objective optimization for XNOR/OR-based Fixed Polarity Reed-Muller (FPRM) logic circuits, this paper proposes an Experience Interaction Mechanism-based Area and Power Co-optimization method (EIM-APCO). At its core is the Dynamic Intelligent Experience-based Dung Beetle Optimizer (DIEDBO), which incorporates three complementary strategies: a dual-mode adaptive exploration strategy that balances global and local search via dynamic mode switching; a jump-based exploitation strategy that uses adaptive step sizes to escape local optima; and a phase-aware intelligent experience fusion strategy that facilitates information sharing and co-evolution within the population. Extensive experiments on 12 MCNC benchmark circuits—including orthogonal parameter tuning, ablation studies, HV indicator analysis, runtime comparison, and Wilcoxon statistical tests—demonstrate that DIEDBO outperforms DBO, MMODE_SPDN, MOGWO, IMOPSO, and MOEA/D, achieving maximum area and power savings of 42.58% and 23.33%, respectively, with an average runtime saving of 45.87%. The results confirm the effectiveness and competitiveness of the proposed method in multi‑objective FPRM circuit optimization.
Authors
- Zhisheng Huo (ORCID: https://orcid.org/0000-0002-5366-0892)
- Limin Xiao (ORCID: https://orcid.org/0000-0002-9806-5851)
- Zhenxue He (ORCID: https://orcid.org/0000-0001-7041-8582)
- Yijin Wang (ORCID: https://orcid.org/0000-0003-3633-4670)
- Lixin Miao (ORCID: https://orcid.org/0009-0008-3213-6857)
- Xiaojun Zhao
- Xiaodan Zhang (ORCID: https://orcid.org/0000-0001-5248-4287)
Institutions
- Hebei Agricultural University (CN)
- Beihang University (CN)
Publication Details
- Journal
- ACM Transactions on Design Automation of Electronic Systems
- Published
- 2026-09-24
- DOI
- https://doi.org/10.1145/3841480
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00