Design of a 3D Aggregation Backbone Network-on-Chip Architecture for High-Speed Data Acquisition Systems

Time-interleaved high-speed data acquisition (HS-DAQ) systems based on three-dimensional network-on-chip (3D NoC) architectures require efficient transmission of multi-channel sampled data. However, existing general-purpose NoC architectures are not well suited for the deterministic multi-source aggregation communication pattern of HS-DAQ systems, which may result in increased long-distance transmission overhead and localized traffic congestion. To address these issues, this paper proposes a 3D aggregation backbone network-on-chip architecture (3D AB-NoC) for HS-DAQ systems. This architecture is based on a 3D Mesh structure and enables the rapid transmission of long-distance aggregated data by establishing coarse-grained aggregation backbone subnets between defined aggregation routing nodes. Furthermore, a Backbone-Boosted XYZ (BB-XYZ) routing algorithm is proposed, which selects the next hop based on the remaining transmission distance of both the basic mesh path and the backbone path, thereby achieving coordinated routing for both local transmission and long-distance aggregation. Simulation results based on the Access Noxim platform demonstrate that the 3D AB-NoC maintains stable basic communication performance under general communication scenarios. In HS-DAQ communication scenarios, the proposed architecture reduces average latency by up to approximately 44%, improves throughput by approximately 29.3%, and significantly suppresses the growth of maximum latency under high-load conditions.