A Dual-Mode Switchable Wide Decimation Range CIC Filter for Sigma–Delta ADCs

This paper presents a dual-mode switchable cascaded integrator-comb (CIC) filter with a wide decimation range for sigma–delta analog-to-digital converters (ADCs), enabling flexible adjustment of the output frequency rate and bandwidth. The proposed filter features two modes that can be switched according to power and precision requirements. In the low-power mode, a standalone CIC filter is adopted to reduce power consumption. A novel three-stage cascade is proposed in the high-precision mode, which consists of a gain-corrected sharpened CIC (GSCIC) filter, a compensation filter, and a half-band filter, so as to enhance the stopband attenuation of the CIC filter and thereby more effectively suppress noise. Meanwhile, the number of multipliers is reduced by half through hardware reuse. The filter is verified through functional simulation on an FPGA. Furthermore, the back-end flow from logic synthesis to layout generation is completed in a 0.18 μm standard CMOS process, achieving an area of 2.89 mm2, power consumption of 0.11 mW in the low-power mode and 0.68 mW in the high-precision mode, and a peak SNR of 133.1 dB. With a flexibly configurable decimation factor ranging from 128 to 4096, the proposed filter can meet the requirements of brain–computer interface or audio signal processing applications with varying bandwidth demands.